NS32FX16-15 Datasheet, PDF (64/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

4 0 Device Specifications (Continued)
4 4 2 2 Input Signal Requirements NS32FX16-15 NS32FX16-20 and NS32FX16-25 (Continued)
Symbol Figure Description
Reference
Conditions
t_PWR
4-18
Power Stable to
RSTI R E
(Note 2)
After V_CC Reaches 4 5V
t_RSTw 4-19 RSTI Pulse Width At 0 8V (Both Edges)
t_INTh
4-16 INT Signal Hold After R E CTTL T2 of
Interrupt Acknowledge Cycle
t_NMIs
t_NMIh
t_SPCd
4-17
4-17
4-12
NMI Setup Time
NMI Hold Time
SPC Pulse Delay
from Slave
(Note 2)
Before F E CTTL
After F E CTTL
After F E CTTL T4
t_SPCs
t_SPCh
t_ADSs
4-12
4-12
4-9
SPC Input Setup
SPC Hold Time
ADS Input Setup
Before R E CTTL
After R E CTTL
Before F E CTTL
t_ADSh
4-9 ADS Input Hold After F E CTTL T1
(Note 3)
t_DDINs
4-9 DDIN Input Setup Before F E CTTL
t_DDINih 4-9 DDIN Input Hold After R E CTTL T4
Note 1 t_Dih is always less than or equal to t_RDia
Note 2 Not tested guaranteed by design
Note 3 ADS must be deasserted before state T4 of the DMA controller cycle
NS32FX16-15
Min Max
50
64
0
15
2
2
22
2
15 t_CTpb3
2
15
2
NS32FX16-20
Min Max
40
64
0
14
2
2
21
2
14 t_CTpb3
2
14
2
NS32FX16-25 _Units
Min Max
30
ms
64
t_CTp
0
ns
12
ns
2
ns
2
t_CTp
20
ns
2
ns
12 t_CTpb3 ns
2
ns
12
ns
2
ns
64