NS32FX16-15 Datasheet, PDF (49/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

3 0 Functional Description (Continued)
Cycle
Status
Interrupt Acknowledge
1
0100
TABLE 3-6 Interrupt Sequences
Address
DDIN
HBE
A0
High Bus
A Non-Maskable Interrupt Control Sequence
FFFF00₁₆
0
1
0
Don’t Care
Interrupt Return
None Performed through Return from Trap (RETT) instruction
Low Bus
Don’t Care
Interrupt Acknowledge
1
0100
B Non-Vectored Interrupt Control Sequence
FFFE00₁₆
0
1
0
Don’t Care
Interrupt Return
None Performed through Return from Trap (RETT) instruction
Don’t Care
Interrupt Acknowledge
1
0100
C Vectored Interrupt Sequence Non-Cascaded
FFFE00₁₆
0
1
0
Don’t Care
Vector
Range 0 – 127
Interrupt Return
1
0110
FFFE00₁₆
0
1
0
Don’t Care
Vector Same as
in Previous Int
Ack Cycle
Interrupt Acknowledge
1
0100
D Vectored Interrupt Sequence Cascaded
FFFE00₁₆
0
1
0
Don’t Care
Cascade Index
range b16 to b1
(The CPU here uses the Cascade Index to find the Cascade Address )
2
0101
Cascade
0
1 or
0 or
Address
0
1
Vector range 0 – 255 on appropriate
half or Data Bus for even odd
address
Interrupt Return
1
0110
FFFE00₁₆
0
1
0
Don’t Care
Cascade Index
same as in
previous Int
Ack Cycle
(The CPU here uses the Cascade Index to find the Cascade Address )
2
0111
Cascade
0
1 or
0 or
Don’t Care
Don’t Care
Address
0
1
If the Cascaded ICU Address is Even (A0 is low) then the CPU applies HBE high and reads the vector number from bits 0–7 of the Data Bus
If the address is Odd (A0 is high) then the CPU applies HBE low and reads the vector number from bits 8–15 of the Data Bus The vector number may be in the
range 0–225
49