UPD78F4216A Datasheet, PDF (9/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
• 100-pin plastic QFP (14 × 20)
µPD78F4216AGF-3BA, µPD78F4218AGF-3BA, µPD78F4216AYGF-3BA, µPD78F4218AYGF-3BA
P60/A16
P61/A17
P62/A18
P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
VDD
P100/TI5/TO5
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/TI00
P36/TI01
P37/EXA^{Note 5}
VPP^{Note 1}
P90
P91
P92
P93
P94
P95
P120/RTP0
P121/RTP1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P84/A4
P83/A3
P82/A2
P81/A1
P80/A0
P27/SCK0/SCL0^{Note 4}
P26/SO0
P25/SI0/SDA0^{Note 4}
P24/BUZ
P23/PCL
P22/ASCK1/SCK1
P21/TxD1/SO1
P20/RxD1/SI1
P72/ASCK2/SCK2
P71/TxD2/SO2
P70/RxD2/SI2
AVREF1
P131/ANO1
P130/ANO0
AVSS^{Note 3}
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVREF0
AVDD^{Note 2}
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the
VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while
mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.
5. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00
9