UPD78F4216A Datasheet, PDF (27/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Main System Clock Oscillator Characteristics (TA = −40 to +85°C)
Resonator
Ceramic
resonator
or crystal
resonator
Recommended Circuit
X2 X1 VSS
Parameter
Oscillation frequency
(fX)
Conditions
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
1.9 V ≤ VDD < 2.0 V
MIN.
2
2
2
2
TYP.
MAX.
12.5
6.25
3.125
2
Unit
MHz
External
clock
X1 input frequency (fX) 4.5 V ≤ VDD ≤ 5.5 V
2
2.7 V ≤ VDD < 4.5 V
2
2.0 V ≤ VDD < 2.7 V
2
X2
X1
1.9 V ≤ VDD < 2.0 V
2
µ PD74HCU04
X1 input high-/low-
15
level width (tWXH, tWXL)
X1 input rising/falling 4.5 V ≤ VDD ≤ 5.5 V
0
time (tXR, tXF)
2.7 V ≤ VDD < 4.5 V
0
2.0 V ≤ VDD < 2.7 V
0
1.9 V ≤ VDD < 2.0 V
0
12.5
6.25
3.125
2
250
MHz
ns
5
ns
10
20
30
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched back to the main system clock after the oscillation
stabilization time is secured by the program.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14125EJ1V0DS00
27