UPD78F4216A Datasheet, PDF (40/60 Pages) NEC – MOS INTEGRATED CIRCUIT

Timing Waveforms
(1) Read operations
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(CLK)
A0 to A7
(Output)
tCYK
Lower address
Lower address
A8 to A19
(Output)
AD0 to AD7
(I/O)
ASTB
(Output)
RD
(Output)
WAIT
(Input)
Hi-Z
Higher address
tDAID
tDSTID
Lower address
Hi-Z
(Output)
tSAST
tHSTLA
tFAR
Data (Input)
tHRID
tWSTH
tDSTR
tDAR
tDAWT
tDRWTL
tDRID
tWRL
tDRWTH
tHRWT
tDWTR
tDWTID
Higher address
tHRA
tDRA
Hi-Z
Lower address
(Output)
tDRST
tDSTWT
tDSTWTH
tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
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Data Sheet U14125EJ1V0DS00