UPD78F4216A Datasheet, PDF (34/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics
(2) External wait timing
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input time from address to
WAIT↓
Input time from ASTB↓ to
WAIT↓
Hold time from ASTB↓ to WAIT
Delay time from ASTB↓ to
WAIT↑
Input time from RD↓ to WAIT↓
Hold time from RD↓ to WAIT↓
Delay time from RD↓ to WAIT↑
Data input time from WAIT↑
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
Input time from WR↓ to WAIT↓
Hold time from WR↓ to WAIT
Delay time from WR↓ to WAIT↑
tDAWT
tDSTWT
tHSTWT
tDSTWTH
tDRWTL
tHRWT
tDRWTH
tDWTID
tDWTR
tDWTW
tDWWTL
tHWWT
tDWWTH
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
(0.5 + n)T + 5
(0.5 + n)T + 10
(0.5 + n)T + 30
nT + 5
nT + 10
nT + 30
0.5T
0.5T
0.5T + 5
0.5T
0.5T
0.5T + 5
nT + 5
nT + 10
nT + 30
(2 + a)T − 40
ns
(2 + a)T − 60
ns
(2 + a)T − 300
ns
1.5T − 40
ns
1.5T − 60
ns
1.5T − 260
ns
ns
ns
ns
(1.5 + n)T − 40
ns
(1.5 + n)T − 60
ns
(1.5 + n)T − 90
ns
T − 40
ns
T − 60
ns
T − 70
ns
ns
ns
ns
(1 + n)T − 40
ns
(1 + n)T − 60
ns
(1 + n)T − 90
ns
0.5T − 5
ns
0.5T − 10
ns
0.5T − 30
ns
ns
ns
ns
ns
ns
ns
T − 40
ns
T − 60
ns
T − 90
ns
ns
ns
ns
(1 + n)T − 40
ns
(1 + n)T − 60
ns
(1 + n)T − 90
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
34
Data Sheet U14125EJ1V0DS00