UPD78F4216A Datasheet, PDF (39/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Data Retention Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Data retention voltage
Data retention current
VDD rise time
VDD fall time
VDD hold time
(from STOP mode setting)
STOP release signal input time
Oscillation stabilization wait time
Low-level input voltage
High-level input voltage
Symbol
Conditions
VDDDR STOP mode
IDDDR VDDDR = 5.0 V ±10%
VDDDR = 2.0 V ±5%
tRVD
tFVD
tHVD
tDREL
tWAIT
VIL
VIH
Crystal resonator
Ceramic resonator
RESET, P00/INTP0 to P06/INTP6
MIN.
TYP.
MAX.
Unit
1.9
5.5
V
10
50
µA
2
10
µA
200
µs
200
µs
0
ms
0
30
5
0
0.9VDDDR
ms
ms
ms
0.1VDDDR
V
VDDDR
V
AC Timing Test Points
VDD − 1 V
0.45 V
0.8VDD or 1.9 V
0.8 V
Test points
0.8VDD or 1.9 V
0.8 V
Data Sheet U14125EJ1V0DS00
39