UPD78F4216A Datasheet, PDF (37/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Other Operations (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
NMI high-/low-level width
Interrupt input high-/low-level width
RESET high-/low-level width
Symbol
Conditions
tWNIL
tWNIH
tWITL
tWITH
INTP0 to INTP6
tWRSL
tWRSH
MIN. TYP. MAX. Unit
10
µs
100
ns
10
µs
Clock Output Operation (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
PCL cycle time
PCL high-/low-level width
PCL rise/fall time
Symbol
Conditions
tCYCL 4.5 V ≤ VDD ≤ 5.5 V, nT
tCLL 4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10
tCLH
tCLR 4.5 V ≤ VDD ≤ 5.5 V
tCLF _{2.7 V ≤ VDD < 4.5 V}
1.9 V ≤ VDD < 2.7 V
MIN.
80
30
TYP. MAX. Unit
31,250 ns
15,615 ns
5
ns
10
ns
20
ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)
n: Divided frequency ratio set by software in the CPU
• When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128
• When using the subsystem clock: n = 1
Data Sheet U14125EJ1V0DS00
37