UPD78F4216A Datasheet, PDF (8/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
2. PIN CONFIGURATION (TOP VIEW)
• 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD78F4216AGC-8EU, µPD78F4218AGC-8EU, µPD78F4216AYGC-8EU, µPD78F4218AYGC-8EU
P120/RTP0
P121/RTP1
P122/RTP2
P123/RTP3
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7
VDD
X2
X1
VSS
XT2
XT1
RESET
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
AVDD^{Note 2}
AVREF0
P10/ANI0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P62/A18
P61/A17
P60/A16
VSS
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P84/A4
P83/A3
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the
VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while
mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.
5. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
8
Data Sheet U14125EJ1V0DS00