UPD78F4216A Datasheet, PDF (33/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics
(1) Read/write operation (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Address active time from RD↑ tDRA
VDD = 5.0 V ±10%
0.5T − 2
ns
VDD = 3.0 V ±10%
0.5T − 12
ns
VDD = 2.0 V ±5%
0.5T − 35
ns
Delay time from RD↑ to ASTB↑ tDRST VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 40
ns
RD low-level width
tWRL
VDD = 5.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 30
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 25
ns
Delay time from address to WR↓ tDAW
VDD = 5.0 V ±10%
(1 + a)T − 24
ns
VDD = 3.0 V ±10%
(1 + a)T − 34
ns
VDD = 2.0 V ±5%
(1 + a)T − 70
ns
Address hold time (from WR↑) tHRD
VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±5%
0.5T − 14
ns
Delay time from ASTB↓ to data tDSTOD
output
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
0.5T + 15
ns
0.5T + 30
ns
VDD = 2.0 V ±5%
0.5T + 240
ns
Delay time from WR↓ to data tDWOD
output
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
0.5T − 30
ns
0.5T − 30
ns
0.5T − 30
ns
Delay time from ASTB↓ to WR↓ tDSTW VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 20
ns
Data setup time (to WR↑)
tSODWR VDD = 5.0 V ±10%
(1.5 + n)T − 20
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 70
ns
Data hold time (from WR↑)
tHWOD VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±5%
0.5T − 50
ns
Delay time from WR↑ to ASTB↑ tDWST VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 30
ns
WR low-level width
tWWL
VDD = 5.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 30
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 30
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
Data Sheet U14125EJ1V0DS00
33