UPD78F4216A Datasheet, PDF (35/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Serial Operation (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
(a) 3-wire serial I/O mode (SCK: Internal clock output)
Parameter
SCK cycle time
SCK high-/low-level width
SI setup time (to SCK↑)
SI hold time (from SCK↑)
SO output delay time
(from SCK↓)
Symbol
Conditions
tKCY1 2.7 V ≤ VDD ≤ 5.5 V
tKH1,
tKL1
tSIK1
2.7 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
tKSI1
tKSO1
MIN. TYP. MAX. Unit
800
ns
3,200
ns
350
ns
1,500
ns
10
ns
30
ns
40
ns
30
ns
(b) 3-wire serial I/O mode (SCK: External clock input)
Parameter
SCK cycle time
SCK high-/low-level width
SI setup time (to SCK↑)
SI hold time (from SCK↑)
SO output delay time
(from SCK↓)
Symbol
Conditions
tKCY2 2.7 V ≤ VDD ≤ 5.5 V
tKH2 2.7 V ≤ VDD ≤ 5.5 V
tKL2
tSIK2 2.7 V ≤ VDD ≤ 5.5 V
tKSI2
tKSO2
MIN. TYP. MAX. Unit
800
ns
3,200
ns
400
ns
1,600
ns
10
ns
30
ns
40
ns
30
ns
(c) UART mode
Parameter
ASCK cycle time
ASCK high-/low-level width
Symbol
Conditions
tKCY3 4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
tKH3 4.5 V ≤ VDD ≤ 5.5 V
tKL3 _{2.7 V ≤ VDD < 4.5 V}
MIN. TYP. MAX. Unit
417
ns
833
ns
1,667
ns
208
ns
416
ns
833
ns
Data Sheet U14125EJ1V0DS00
35