UPD78F4216A Datasheet, PDF (32/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
Cycle time
tCYK
4.5 V ≤ VDD ≤ 5.5 V
80
2.7 V ≤ VDD < 4.5 V
160
2.0 V ≤ VDD < 2.7 V
320
1.9 V ≤ VDD < 2.0 V
500
Address setup time (to ASTB↓) tSAST VDD = 5.0 V ±10%
(0.5 + a)T − 20
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
(0.5 + a)T − 40
(0.5 + a)T − 80
Address hold time (from ASTB↓) tHSTLA VDD = 5.0 V ±10%
0.5T − 19
VDD = 3.0 V ±10%
0.5T − 24
VDD = 2.0 V ±5%
0.5T − 34
ASTB high-level width
tWSTH VDD = 5.0 V ±10%
(0.5 + a)T − 17
VDD = 3.0 V ±10%
(0.5 + a)T − 40
Address hold time (from RD↑) tHRA
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
(0.5 + a)T − 110
0.5T − 14
VDD = 3.0 V ±10%
0.5T − 14
VDD = 2.0 V ±5%
0.5T − 14
Delay time from address to RD↓ tDAR
VDD = 5.0 V ±10%
(1 + a)T − 24
VDD = 3.0 V ±10%
(1 + a)T − 35
VDD = 2.0 V ±5%
(1 + a)T − 80
Address float time (from RD↓) tFAR
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
Data input time from address
tDAID
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
Data input time from ASTB↓
tDSTID VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
Data input time from RD↓
tDRID
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
Delay time from ASTB↓ to RD↓ tDSTR VDD = 5.0 V ±10%
0.5T − 9
VDD = 3.0 V ±10%
0.5T − 9
Data hold time (from RD↑)
tHRID
VDD = 2.0 V ±5%
VDD = 5.0 V ±10%
0.5T − 20
0
VDD = 3.0 V ±10%
0
VDD = 2.0 V ±5%
0
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of waits (n ≥ 0)
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
0
ns
0
ns
(2.5 + a + n)T − 37 ns
(2.5 + a + n)T − 52 ns
(2.5 + a + n)T − 120 ns
(2 + n)T − 35
ns
(2 + n)T − 50
ns
(2 + n)T − 80
ns
(1.5 + n)T − 40
ns
(1.5 + n)T − 50
ns
(1.5 + n)T − 90
ns
ns
ns
ns
ns
ns
ns
32
Data Sheet U14125EJ1V0DS00