UPD78F4216A Datasheet, PDF (36/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(d) I²C bus mode
Parameter
Symbol
SCL0 clock frequency
fCLK
Bus free time (between stop
and start conditions)
Hold time^Note1
tBUF
tHD : STA
Low-level width of SCL0 clock
tLOW
High-level width of SCL0 clock tHIGH
Setup time of start/restart
conditions
tSU : STA
Data hold
time
When using CBUS-
compatible master
When using I²C bus
tHD : DAT
Data setup time
tSU : DAT
Rise time of SDA0 and SCL0
tR
signals
Fall time of SDA0 and SCL0
tF
signals
Setup time of stop condition
tSU : STO
Pulse width of spike restricted
tSP
by input filter
Load capacitance of each bus
Cb
line
Standard Mode
MIN.
MAX.
0
100
4.7
−
4.0
−
4.7
−
4.0
−
4.7
−
5.0
0^{Note 2}
250
−
−
−
−
1,000
−
300
4.0
−
−
−
−
400
High-Speed Mode
Unit
MIN.
MAX.
0
400
kHz
1.3
−
µs
0.6
−
µs
1.3
−
µs
0.6
−
µs
0.6
−
µs
−
−
µs
0^{Note 2}
0.9^{Note 3}
µs
100^{Note 4}
−
ns
20 + 0.1Cb^{Note 5}
300
ns
20 + 0.1Cb^{Note 5}
300
ns
0.6
−
µs
0
50
ns
−
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time.
2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on VIHmin.) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold
time tHD : DAT needs to be satisfied.
4. The high-speed mode I²C bus can be used in a standard mode I²C bus system. In this case, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low-level hold time
tSU : DAT ≥ 250 ns
• If the device extends the SCL0 signal low-level hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : DAT
= 1,000 + 250 = 1,250 ns by standard mode I²C bus specification)
5. Cb: Total capacitance per bus line (unit: pF)
36
Data Sheet U14125EJ1V0DS00