UPD78F4216A Datasheet, PDF (38/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
A/D Converter Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
Resolution
Overall error^{Notes 1, 2}
2.7 V ≤ VDD ≤ 5.5 V
2.2 V ≤ AVREF0 ≤ VDD
1.9 V ≤ VDD < 2.7 V
1.9 V ≤ AVREF0 ≤ VDD
Conversion time
tCONV
Sampling time
tSAMP
Analog input voltage
VIAN
Reference voltage
AVREF0
Resistance between AVREF0 and AVSS RAVREF0 When not A/D converting
MIN.
8
TYP.
8
MAX. Unit
8
bits
±1.2 %FSR
±1.6 %FSR
14
24/fXX
AVSS
1.9
144
µs
µs
AVREF0
V
AVDD
V
40
kΩ
Notes 1. Quantization error (±1/2 LSB) is not included.
2. Overall error is indicated as a ratio to the full-scale value.
Remark fXX : Main system clock frequency
D/A Converter Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Resolution
Overall error^{Notes 1, 2}
Settling time
Output resistance
Reference voltage
AVREF1 current
Symbol
Conditions
R = 10 MΩ, 2.0 V ≤ AVREF1 ≤ VDD,
2.0 V ≤ VDD ≤ 5.5 V
R = 10 MΩ, 1.9 V ≤ AVREF1 ≤ VDD,
1.9 V ≤ VDD ≤ 2.0 V
Load conditions:
C = 30 pF
4.5 V ≤ AVREF1 ≤ 5.5 V
2.7 V ≤ AVREF1 < 4.5 V
1.9 V ≤ AVREF1 < 2.7 V
RO DACS0, 1 = 55H
AVREF1
AIREF1 For only 1 channel
MIN.
8
TYP.
8
MAX. Unit
8
Bits
±0.6 %FSR
±1.2 %FSR
10
µs
15
µs
20
µs
8
kΩ
1.9
VDD
V
2.5
mA
Notes 1. Quantization error (±1/2 LSB) is not included.
2. Overall error is indicated as a ratio to the full-scale value.
38
Data Sheet U14125EJ1V0DS00