UPD78F4216A Datasheet, PDF (28/60 Pages) NEC – MOS INTEGRATED CIRCUIT

µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C)
Resonator
Crystal
resonator
Recommended Circuit
VSS XT2 XT1
Parameter
Oscillation frequency
(fXT)
Oscillation
stabilization time^Note
Conditions
4.5 V ≤ VDD ≤ 5.5 V
1.9 V ≤ VDD < 4.5 V
MIN.
TYP. MAX.
Unit
32
32.768
35
kHz
1.2
2
s
10
External
clock
XT2 XT1
µ PD74HCU04
XT1 input frequency
(fXT)
XT1 input high-/low-
level width (tXTH, tXTL)
32
35
kHz
14.3
15.6
µs
Note Time required to stabilize oscillation after applying supply voltage (VDD).
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
28
Data Sheet U14125EJ1V0DS00