MT9V112 Datasheet, PDF (9/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Figure 4: 36-Ball ICSP Assignment
1
2
3
4
5
6
A
VDD
DOUT3 DOUT5 DOUT7 CLKIN
VDD
B
DOUT0
DGND
DOUT4
DOUT6
VDDQ
LINE
_VALID
C
DOUT1 DOUT2 DGND
DGND
FRAME
_VALID
VDD
D
DOUT
DOUT
DGND
DGND
TEST
VAA
_LSB0 _LSB1
_ENABLE
E
SADDR VDDQ STROBE RESET# DGND AGND
F
VDD
PIXCLK SCLK
STAND
BY
SDATA VAAPIX
Top View
(Ball Down)
Table 2: Ball Description
BALL
ASSIGNMENT
A5
E4
E1
D5
F3
F4
NAME
CLKIN
RESET#
SADDR
TEST_ENABLE
SCLK
STANDBY
TYPE
Input
Input
Input
Input
Input
Input
F5
B1, C1, C2, A2,
B3, A3, B4, A4
D1
SDATA
DOUT(7:0)
DOUT_LSB0
Output
Output
Output
D2
DOUT_LSB1
Output
C5
B6
F2
E3
E6
B2, C3, C4, D3,
D4, E5
FRAME_VALID
LINE_VALID
PIXCLK
STROBE
AGND
DGND
Output
Output
Output
Output
Supply
Supply
DESCRIPTION
Master clock in sensor.
Active LOW: asynchronous reset.
Two-Wire Serial Interface Device ID selection 1:0xBA, 0:0x90.
Tie to DGND for normal operation. (Manufacturing use only.)
Two-Wire Serial Interface Clock.
Multifunctional signal to control device addressing, power-down, and
state functions (covering output enable function).
Two-Wire Serial Interface Data I/O.
Pixel Data Output bit 0, DOUT(7) (most significant bit (MSB)), DOUT(0)
(least significant bit (LSB)).
Sensor bypass mode output 0—typically left unconnected for normal SOC
operation.
Sensor bypass mode output 1—typically left unconnected for normal SOC
operation.
Active HIGH: FRAME_VALID; indicates active frame.
Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel.
Pixel clock output.
Active HIGH: strobe (Xenon) or turn on (LED) flash.
Analog ground.
Core digital ground.
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
9
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