MT9V112 Datasheet, PDF (42/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT
(HEX)
Bit 7
Enable Xenon flash. Same physical register as Reg0x023, bit 13.
Xenon Flash
Enable
Bit 3
Read Mode
Select
0: Use READ mode, context A, Reg0x021.
1: Use READ mode, context B, Reg0x020.
Note that bits found only in the READ mode context B register is
always taken from that register.
Bit 2
LED Flash
Enable
Enable LED flash. Same physical register as Reg0x023, bit 8.
Bit 1
Vertical
Blanking
Select
0: Use vertical blanking, context A, Reg0x008.
1: Use vertical blanking, context B, Reg0x006.
Bit 0
Horizontal
Blanking
Select
0: Use horizontal blanking, context A, Reg0x007.
1: Use horizontal blanking, context B, Reg0x005.
R240:0—0x0F0 – Page Map
Bits 2:0
Page Map
Page mapping register. Must be kept at 0 to be able to WRITE
to/READ from sensor. Used in the SOC to access other pages with
registers.
R241:0—0x0F1 – Byte-Wise Address
Bit 0
Byte-Wise
Address
Special address to perform 8-bit (instead of 16-bit) READs and
WRITEs to the sensor. For additional information, see “Two-
Wire Serial Interface Sample” on page 54 and “Appendix A” on
page 52.
R255:0—0x000 – Chip Version (R/O)
Bits 15:0 Hardwired READ only.
0x0
0x1
0x0
0x1
0x1
0x0
N/A
0x1229
SYNC’D TO
FRAME
START
Y
Y
Y
Y
Y
N
0
BAD READ/
FRAME WRITE
N
W
YM
W
Y
W
YM
W
YM
W
0
W
0
0
R
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
42
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