MT9V112 Datasheet, PDF (41/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT
(HEX)
Bit 9
0: Flash should be enabled for one frame only.
Every Frame 1: Flash should be enabled every frame.
Bit 8
LED Flash
Enables LED flash. When set, the FLASH_STROBE goes on prior
to the start of a frame reset. When disabled, the FLASH_STROBE
remains HIGH until readout of the current frame completes.
Bits 7:0
Xenon
Count
Length of FLASH_STROBE pulse when Xenon flash is enabled.
The value specifies the length in 1,024 master clock cycle
increments.
R43:0—0x02B – Green1 Gain
Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) (Bit 11 + 1) x analog gain
Digital Gain (each bit gives 2x gain).
Bits 8:7
Analog
Gain
Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives
2x gain).
Bits 6:0
Initial gain = bits (6:0) x 0.03125.
Initial Gain
R44:0—0x02C – Blue Gain
Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) (Bit 11 + 1) x analog gain
Digital Gain (each bit gives 2x gain).
Bits 8:7
Analog
Gain
Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives
2x gain).
Bits 6:0
Initial gain = bits (6:0) x 0.03125.
Initial Gain
R45:0—0x02D – Red Gain
Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) x (Bit 11 + 1) x analog gain
Digital Gain (each bit gives 2x gain).
Bits 8:7
Analog
Gain
Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives
2x gain).
Bits 6:0
Initial gain = bits (6:0) x 0.03125.
Initial Gain
R46:0—0x02E – Green2 Gain
Bits 11:9 Total gain = (Bit 9 + 1) x (Bit 10 + 1) x (Bit 11 + 1) x analog gain
Digital Gain (each bit gives 2x gain).
Bits 8:7
Analog
Gain
Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives
2x gain).
Bits 6:0
Initial gain = bits (6:0) x 0.03125.
Initial Gain
R47:0—0x02F – Global Gain
Bits 11:0 This register can be used to set all four gains at once. When
Global Gain read, it returns the value stored in Reg0x2B.
R200:0—0x0C8 – Context Control
Bit 15
Restart
Setting this bit causes the sensor to abandon the current frame
and start resetting the first row. Same physical register as
Reg0x00D, bit 1.
0x1
0x0
0x08
0x0
0x0
0x20
0x0
0x0
0x20
0x0
0x0
0x20
0x0
0x0
0x20
0x20
0x0
SYNC’D TO
FRAME
START
N
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
BAD READ/
FRAME WRITE
N
W
Y
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
N
W
YM
W
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
41
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