MT9V112 Datasheet, PDF (39/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT
(HEX)
Bit 5
This reset signal is fed directly to the SOC part of the chip, and
0x0
Reset SOC has no functionality in a stand alone sensor.
Bit 4
When set, the output signals are tri-stated.
0x0
Output
Disable
Bit 3
0: Stop sensor readout.
0x1
Chip Enable When this is returned to “1,” sensor readout restarts and begins
resetting the starting row in a new frame. To reduce the digital
power, the master clock to the sensor can be disabled or
STANDBY can be used.
1: Normal operation.
Bit 2
0: Normal operation (default)
0x0
Standby 1: Disable analog circuitry and internal clocks. Whenever this bit
is set to “1” the chip enable bit (bit 3) should be set to “0.”
Bit 1
Restart
Setting this bit causes the sensor to abandon the current frame
0x0
and start resetting the first row. The delay before the first valid
frame is read out equals the integration time. This bit always
reads “0.”
Bit 0
Reset
Setting this bit puts the sensor in reset mode; this sets the sensor 0x0
to its default power-up state. Clearing this bit resumes normal
operation.
R32:0—0x020 – Read Mode—Context B
Bit 15
0: LINE_VALID determined by bit 9.
0x0
XOR Line Ineffective if Continuous LINE_VALID is set.
Valid
1: LINE_VALID = “Continuous” Line Valid XOR Frame Valid,
Bit 14
0: Normal LINE_VALID (default, no line valid during vertical
0x0
Continuous blanking).
Line Valid 1: “Continuous” LINE_VALID (continue producing line valid
during vertical blanking).
Bit 10
When READ mode context B is selected (bit 3, Reg0x0C8 = 1):
0x1
Low-Power 0: Full power, maximum readout speed.
Mode—
1: Low power. Maximum readout frequency is now half of the
Context B master clock, and the pixel clock is automatically adjusted as
described for the pixel clock speed register.
Bit 9
Show
Border
This bit indicates whether to show the border enabled by bit 8.
0x1
When bit 8 is 0, this bit has no meaning. When bit 8 is 1, this bit
decides whether the border pixels should be treated as extra
active pixels (1) or extra blanking pixels (0).
Bit 8
When this bit is set, a 4-pixel border is output around the active 0x1
Over Sized image array independent of readout mode (skip, zoom, mirror,
etc.). Setting this bit therefore adds eight to the numbers of
rows and columns in the frame.
Bits 7:6
Reserved.
0x0
SYNC’D TO
FRAME
START
N
N
N
N
N
N
N
N
Y
N
Y
Y
BAD READ/
FRAME WRITE
0
W
0
W
YM
W
YM
W
YM
W
YM
W
0
W
0
W
YM
W
0
W
YM
W
YM
W
Bit 5
0: Normal readout.
0x0
Column
1: READ out two columns, and then skip six columns (as with
Skip 4x
rows).
Bit 4
0: Normal readout.
0x0
Row Skip 4x 1: READ out two rows, and then skip six rows (i.e., row 8, row 9,
row 16, row 17…).
Y
YM
W
Y
YM
W
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.