MT9V112 Datasheet, PDF (38/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT
(HEX)
Bits 7:4
Delay PIXCLK in half-master-clock cycles. When set, the pixel
0x1
Delay Pixel clock can be delayed in increments of half-master- clock cycles
Clock
compared to the synchronization of FRAME_VALID, LINE_VALID,
and DATA_OUT.
Bits 3:0
The pixel clock period is doubled, so the ADC clock period
0x1
Pixel Clock remains the same for one programmed register value. The value
Speed
“0” is not allowed, and “1” is used instead.
R11:0—0x00B – Extra Delay
Bits 13:0 Extra blanking inserted between frames specified in pixel clocks. 0x0
Extra Delay Can be used to get a more exact frame rate. For integration
times less than a frame, however, it might affect the integration
times for parts of the image.
R12:0—0x00C – Shutter Delay
Bits 10:0 The amount of time from the end of the sampling sequence to
0x0
Shutter
the beginning of the pixel reset sequence. This variable is
Delay
automatically halved in low-power mode, so the time in use
remains the same. This register has an upper value defined by
the fact that the reset needs to finish prior to readout of that
row to prevent changes in the row time.
R13:0—0x00D – Reset
Bit 15
0: Normal operation, updates changes to registers that affect
0x0
Synchronize image brightness at the next frame boundary (integration time,
Changes integration delay, gain, horizontal blanking and vertical
blanking, window size, row/column skip, or row mirror.
1: Do not update any changes to these settings until this bit is
returned to “0.” All registers that are frame-synchronized are
affected by this bit setting.
Bit 13
Setting this bit turns off all SOC clocks.
0x0
Stop_soc
Bit 12
Div 2
By setting this bit, the CLK_IN is divided by two before going to 0x0
master clock control.
Bit 10
Setting this bit converts SHIP_ID from default to the other
0x0
Switch
(0xBA/0xBB => 0x90/0x91).
Two-wire
Interface ID
Bit 9
When set, a forced restart occurs when a bad frame is detected. 0x0
Restart Bad This can shorten the delay when waiting for a good frame
Frames
because the delay when masking out a bad frame is the
integration time rather than the full frame time.
Bit 8
0: Only output good frames (default)
0x0
Show Bad A bad frame is defined as the first frame following a change to:
Frames
window size or position, horizontal blanking, pixel clock speed,
zoom, row or column skip, or mirroring.
1: Output all frames (including bad frames)
Bit 7
Inhibit
Standby
Setting this bit stops STANDBY from affecting entry to or exit
from the low-power state.
Bit 6
Drive
Signals
By default, asserting STANDBY causes the ball interface to enter
High-Z. Setting this bit stops STANDBY from contributing to
output enable control.
SYNC’D TO
FRAME
START
N
Y
Y
Y
N
N
N
N
N
N
BAD READ/
FRAME WRITE
0
W
YM
W
0
W
N
W
0
W
0
W
0
W
N
W
0
W
0
W
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
38
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