MT9V112 Datasheet, PDF (56/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Two-wire Serial Bus Timing
The two-wire serial interface operation requires a
certain minimum of master clock cycles between tran-
sitions. These are specified below in master clock
cycles.
Figure 19: Serial Host Interface Start
Condition Timing
5
4
SCLK
Figure 21: Serial Host Interface Data
Timing for Write
4
4
SCLK
SDATA
SDATA
Figure 20: Serial Host Interface Stop
Condition Timing
5
4
SCLK
NOTE:
SDATA is driven by an off-chip transmitter.
Figure 22: Serial Host Interface Data
Timing for Read
5
SCLK
SDATA
SDATA
NOTE:
All timing are in units of master clock cycle.
NOTE:
SDATA is pulled LOW by the sensor, or allowed to be
pulled HIGH by a pull-up resistor off-chip.
Figure 23: Acknowledge Signal Timing After an 8-bit Write to the Sensor
6
3
SCLK
SDATA
Sensor pulls down
SDATA pin
Figure 24: Acknowledge Signal Timing After an 8-bit Read from the Sensor
7
6
SCLK
SDATA
Sensor tri-states SDATA pin
(turns off pull down)
NOTE:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is com-
plete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or stop
bit may be used.
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
56
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