MT9V112 Datasheet, PDF (22/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 9: Colorpipe Register Description (continued)
Bit 1
Enables auto white balance.
1: Enables auto white balance.
0: Freezes white balance at current values.
Bit 0
Reserved for future expansion.
R8:1—0X108 – Output Format Control (R/W)
Default
0x0080
Description This register specifies the output timing and format in conjunction with R58:1 or R155:1 (depending on the
context).
Bits 15:11 Reserved for future expansion.
Bit 10
Gate PIXCLK.
0: PIXCLK not gated.
1: PIXCLK gated with LINE_VALID.
Bit 9
Flip Bayer columns in processed Bayer output mode.
0: Column order is green, red and blue, green.
1: Column order is red, green and green, blue.
Bit 8
Flip Bayer row in processed Bayer output mode.
0: First row contains green and red; the second row contains blue and green.
1: First row contains blue and green; the second row contains green and red.
Bit 7
Controls the values used for the protection bits in Rec. ITU-R BT.656 codes.
0: Use zeros for the protection bits.
1: Use the correct values.
Bit 5
Multiplexes Y (in YCbCr mode) or green (in RGB mode) channel on all channels (monochrome).
1: Forces Y/G onto all channels.
Bit 4
Disables Cb color output channel (Cb = 128) in YCbCr mode and disables the blue color output channel
(B = 0) in RGB mode.
1: Forces Cab to 128 or B to 0.
Bit 3
Disables Y color output channel (Y = 128) in YCbCr and disables the green color output channel (G = 0) in
RGB mode.
1: Forces Y to 128 or G to 0.
Bit 2
Disables Cr color output channel (Cr = 128) in YCbCr mode and disables the red color output channel (R = 0)
in RGB mode.
1: Forces Cr to 128 or R to 0.
Bit 1
Toggles the assumptions about Bayer vertical CFA shift.
0: Row containing red comes first.
1: Row containing blue comes first.
Bit 0
Toggles the assumptions about Bayer horizontal CFA shift.
0: Green comes first.
1: Red or blue comes first.
R37:1—0x125 – Color Saturation Control (R/W)
Default
0x0005
Description This register specifies the color saturation control settings.
Bit 5:3
Specify overall attenuation of the color saturation.
“000”—Full color saturation
“001”—75% of full saturation
“010”—50% of full saturation
“011”—37.5% of full saturation
“100”—25% of full saturation
“101”—150% of full saturation
“110”—Black and white
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
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