MT9V112 Datasheet, PDF (50/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
I/O Timing
By default, the MT9V112 launches pixel data,
FRAME_VALID, and LINE_VALID synchronously with
the falling edge of PIXCLK. The expectation is that the
user captures data, FRAME_VALID, and LINE_VALID
using the rising edge of PIXCLK. The timing diagram is
shown in Figure 12. As an option, the polarity of the
PIXCLK can be inverted from the default. This is
achieved by programming R58:1[9] or R155:1[9] to “0.”
Figure 12: I/O Timing
CLKIN
Tclkin_min_high
Tclkinf_pixclkr
Tclkin_min_low
PIXCLK
Tclkinr_pixclkf
Tpixclk_min_high Tpixclk_min_low
DATA[7:0]
FRAME_VALID
LINE_VALID
Tclkinr_dout
Tclkinr_fvlv
Tdout_su Tdout_ho
Tfvlv_su
Tclkin_min_period
Tfvlv_ho
UNDEFINED
Table 21: I/O Timing
SIGNAL
CLKIN
PIXCLK
DATA[7:0]
FRAME_VALID/
LINE_VALID
PARAMETER
Tclkin_min_high
Tclkin_min_low
Tclkin_min_period
Tclkinr_pixclkf
Tclkinf_pixclkfr
Tpixclk_min_low
Tpixclk_min_high
Tclkinr_dout
Tdout_su
Tdout_ho
Tclkinr_fvlv
Tfvlv_su
Tfvlv_ho
CONDITIONS
50:50, 27 MHz CLKIN
50:50, 27 MHz CLKIN
50:50, 27 MHz CLKIN
50:50, 27 MHz CLKIN
50:50, 27 MHz CLKIN
50:50, 27 MHz CLKIN
SLOW
MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
FAST
MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
50
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