MT9V112 Datasheet, PDF (7/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Register Notation
The following register address notations are used in
this document:
• R<decimal address>:<address page>
Example: R9:0—Shutter width register in sensor
page (page 0). Used to uniquely specify a register.
• R<decimal address>
Example: R240—Page address register. Used when
the register address is global in all three pages or
when by context the address page is understood.
• 0x<2 digit hex address>
Example: 0xF0—Page address register. Used when
the register address is global in all three pages, or
when by context the address page is understood.
Figure 1: Functional Block Diagram
SCLK
SDATA
CLKIN
STANDBY
VDDQ/DGND
V DD/DGND
VAA /AGND
VAAPIX
Sensor Core
Pixel Data
. _{640H x 480V}
. _{1/6-inch optical format}
. _{Auto black compensation}
. _{Programmable analog gain}
. _{Programmable exposure}
. _{10-bit ADC}
. _{H/W context switch to/from preview}
. Bayer RGB output
Control Bus
(Two-Wire Serial
Control Bus
Interface Transactions)
(Two-Wire Serial Interface Transactions)
+ Sensor control (gains, shutter, etc.)
SRAM
Line Buffers
Image Flow Processor
Camera Control
Auto exposure
Auto white balance
Flicker detect/avoid
Camera control:
Snapshots, flash, video, clip
Image Flow Processor
Control Bus
Colorpipe
(Two-Wire Serial
Interface
Transactions)
Lens shading correction
Color interpolation
Filtered resize and zoom
Defect correction
Color correction
Image Data ^{Gamma correction}
Color conversion + formatting
DOUT [7:0]
PIXCLK
FRAME_VALID
LINE_ VALID
STROBE
Figure 2: Internal Registers Grouping
Image Flow Processor
Sensor Core
Registers
R[255:0]
Color Pipeline
Registers
R[255:0]
Camera Control
Registers
R[255:0]
Page 0
Page 1
Page 2
NOTE:
Internal registers are grouped in three address spaces. Program R240 selects the desired address space.
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
7
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