MT9V112 Datasheet, PDF (20/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 8: Camera Control Registers – Address Page 2 (continued)
REGISTER
# DEC
(HEX)
204 (CC)
205 (CD)
206 (CE)
207 (CF)
208 (D0)
209 (D1)
210 (D2)
211 (D3)
212 (D4)
213 (D5)
239 (EF)
242 (F2)
243 (F3)
245 (F5)
246 (F6)
255 (FF)
REGISTER NAME
Camera Control Sequencer Parameter 3
Camera Control Sequencer Parameter 4
Camera Control Sequencer Parameter 5
Camera Control Sequencer Parameter 6
Camera Control Sequencer Parameter 7
Camera Control Sequencer Parameter 8
Camera Control Sequencer Parameter 9
Camera Control Sequencer Parameter 10
Camera Control Sequencer Parameter 11
Camera Control Sequencer Parameter 12
AWB Parameter 15
AWB Parameter 16
Reserved
Color Correction Parameter 29
Color Correction Parameter 30
Color Correction Parameter 39
DATA FORMAT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DEFAULT
VALUE DEC
(HEX) MODULE
0 (0000) CntxCtl
2190 (21A0) CntxCtl
7835 (1E9B) CntxCtl
19018(4A4A) CntxCtl
5773 (168D) CntxCtl
77 (004D) CntxCtl
0 (0000) CntxCtl
0 (0000) CntxCtl
520 (0208) CntxCtl
0 (0000) CntxCtl
8 (0008) AWB
0 (0000) AWB
0 (0000) —
135 (0040) ColorCorr
127 (007F) ColorCorr
43136(A880) ColorCorr
NOTE:
Data Format Key:
0 = “Don't Care” bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values.
d = R/W bit
? = R/O bit.
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
20
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