MT9V112 Datasheet, PDF (37/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions
BIT FIELD
DESCRIPTION
DEFAULT
(HEX)
R0:0—0x000 – Chip Version (R/O)
Bits 15:0 Hardwired READ only.
R1:0—0x001 – Row Start
Bits 10:0
Row Start
The first row to be read out (not counting dark rows that may
be read). To window the image down, set this register to the
starting Y value. Setting a value less than 8 is not recommended
since the dark rows should be read using Reg0x022.
R2:0—0x002 – Column Start
Bits 10:0
Col Start
The first column to be read out (not counting dark columns that
may be read). To window the image down, set this register to
the starting X value. Setting a value below 0x18 is not
recommended since readout of dark columns should be
controlled by Reg0x022.
R3:0—0x003 – Row Width
Bits 10:0 Number of rows in the image to be read out (not counting dark
Row Width rows or border rows that may be read).
R4:0—0x004 – Column Width
Bits 10:0 Number of columns in image to be read out (not counting dark
Col Width columns or border columns that may be read).
R5:0—0x005 – Horizontal Blanking—Context B
Bits 10:0 Number of blank columns in a row when context B is chosen (bit
Horizontal 0, Reg0x0C8 = 1). The extra columns are added at the beginning
Blanking B of a row. The minimum supported value is 132.
R6:0—0x006 – Vertical Blanking—Context B
Bits 14:0
Vertical
Blanking B
Number of blank rows in a frame when context B is chosen (bit
1, Reg0x0C8 = 1). This number must be equal to or larger than
the number of dark rows read out in a frame specified by
Reg0x022.
R7:0—0x007 – Horizontal Blanking—Context A
Bits 10:0 Number of blank columns in a row when context A is chosen (bit
Horizontal 0, Reg0x0C8 = 0). The extra columns are added at the beginning
Blanking A of a row. The minimum supported value is 132.
R8:0—0x008 – Vertical Blanking—Context A
Bits 14:0
Vertical
Blanking A
Number of blank rows in a frame when context A is chosen (bit
1, Reg0x0C8 = 1). This number must be equal to or larger than
the number of dark rows read out in a frame specified by
Reg0x022.
R9:0—0x009 – Shutter Width
Bits 15:0
Shutter
Width
Integration time in number of rows. In addition to this register,
the shutter delay register (Reg0x0C) and the overhead time
influences the integration time for a given row time.
R10:0—0x00A – Row Speed
Bit 13
Invert to cb clock.
Bit 8
Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and
Invert Pixel DATA_OUT is set to the falling edge of PIXCLK. When clear, they
Clock
are set to the rising edge if there is no pixel clock delay.
0x1229
0x12
0x26
0x1E0
0x284
0xCB
0x0B
0xCB
0xB
0x1D6
—
0x0
SYNC’D TO
FRAME
START
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
N
BAD READ/
FRAME WRITE
R
YM
W
YM
W
YM
W
YM
W
YM
W
N
W
YM
W
N
W
N
W
—
—
0
W
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
37
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