MT9V112 Datasheet, PDF (24/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 9: Colorpipe Register Description (continued)
Bit 1
In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R155:1.
Bit 0
In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R155:1.
R72:1—0x148 - Test Pattern Generator control (R/W)
Default
0x0000
Description
This register enables test pattern generation at the input of the image processor. Values greater than “0”
turn on the test pattern generator. The brightness of the flat-color areas depends on the value programmed
(from 6–1) in this register. The value 7 produces the color bar pattern. Value 0 selects the sensor image.
Bit 7
Test pattern selection.
Bits 2:0
1: Forces WB digital gains to 1.0.
0: Normal operation.
R153:1—0x199 – Line Counter (R/O)
Default
N/A
Description Use line counter to determine the number of the line currently being output.
Bits 15:0
Line count.
R154:1—0x19A – Frame Counter (R/O)
Default
N/A
Description Use frame counter to determine the index of the frame currently being output.
Bits 15:0
Frame count.
R155:1—0x19B – Output Format Control 2—Context B (R/W)
Default
0x0200
Description Output format control 2—context B.
Bit 14
Output processed Bayer data.
Bit 13
Reserved.
Bit 12
Reserved
Bit 11
Enables embedding Rec. ITU-R BT.656 synchronization codes to the output data. See R58:1.
Bit 10
Entire image processing is bypassed and raw bayer is output directly.
In YCbCr or RGB mode:
0: Normal operation, sensor core data flows through IFP.
1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera
interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2.
Data rate is effectively the same as default 16-bit /per pixel modes. auto exposure/AWB, etc. still function
and control the sensor, though they are assuming some gain/correction through the colorpipe. See R58:1.
Bit 9
Inverts output pixel clock. By default, this bit it asserted and data is launched off the falling edge of PIXCLK
for capture by the receiver on the rising edge. See R58:1.
Bit 8
Enables RGB output.
0: Output YCbCr data.
1: Output RGB format data as defined by R155:1[7:6]. See R58:1.
Bits 7:6
RGB output format:
“00”—16-bit RGB565.
“01”—15-bit RGB555.
“10”—12-bit RGB444x.
“11”—12-bit RGBx444.
Bits 5:4
Test Ramp output:
“00”—Off.
“01”—By column.
“10”—By row.
“11”—By frame.
Bit 3
Output RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth.
Bit 2
Averages two nearby chrominance bytes. See R58:1
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
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