MT9V112 Datasheet, PDF (44/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Modes and Timing
This section provides an overview of typical usage
modes for the MT9V112.
Contexts
The MT9V112 supports hardware-accelerated con-
text switching. A number of parameters have two cop-
ies of their setup registers; this allows two “contexts” to
be loaded at any given time. These are referred to as
context A and context B. Context selection for any sin-
gle parameter is determined by the global context con-
trol register (GCCR, see R200:2). There are copies of
this register in each address page. A WRITE to any one
of them has the identical effect. However, a READ from
address page 0 only returns the subset bits of R200 that
are specific to the sensor core.
Contexts are generically named because they can be
utilized for a variety of purposes. One typical usage
model is to define context A as viewfinder or preview
mode and context B as snapshot mode. The device
defaults are configured with this in mind. This mecha-
nism enables the user to have settings for viewfinder
and snapshot modes loaded at the same time, and
then switch between them with a single WRITE to a
register (e.g., R200:2).
Viewfinder/Preview and Full-
Resolution/Snapshot Modes
No context switching is necessary in the sensor core
because this is a single ADC device. Context switching
occurs in the colorpipe stage.
Preview Mode
QVGA (320 x 240) images are generated at up to 30
fps. The reduced-size images are generated by a scaling
down operation. The sensor always outputs a VGA size
image to the colorpipe in both context A and context B.
Snapshot Mode
VGA (640 x 480) images are generated at up to 30 fps.
This is typically selected by setting R200:n[10] = 1
selecting resize/zoom context B.
Switching Modes
Typically, switching to snapshot mode is achieved
by writing R200:2 = 0x9F0B. This restarts the sensor
and sets most contexts to context B. Following this
WRITE, a READ from R200:1 or R200:2 results in
0x1F0B being read. Note that the MSB is cleared auto-
matically by the sensor. A READ from R200:0 results in
0x000B, as only the lower 4 bits and the restart MSB are
implemented in the sensor core.
Clocks
The sensor core is a master in the system. The sen-
sor core frame rate defines the overall image flow pipe-
line frame rate. Horizontal blanking and vertical
blanking are influenced by the sensor configuration,
and are also a function of certain image flow pipeline
functions—particularly resize. The relationship of the
primary clocks are depicted in Figure 9.
The image flow pipeline typically generates up to
16-bits per pixel—for example, YCbCr or RGB565—but
has only an 8-bit port through which to communicate
this pixel data. There is no phase-locked loop (PLL), so
the primary input clock (CLKIN) must be twice the
fundamental pixel rate (defined by the sensor pixel
clock).
To generate VGA images at 30 fps, the sensor core
requires a clock in the 24 MHz–27 MHz range. The
device defaults assume a 24 MHz clock, and minimum
clock frequency is 2 MHz.
Figure 9: Primary Sensor Core Clock
Relationships
CLKIN
Sensor
Master Clock
Sensor
Pixel Clock
Sensor Core
10 bits/pixel
1 pixel/clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (typical)
0.5 pixel/clock
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
44
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