MT9V112 Datasheet, PDF (40/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT
(HEX)
Bit 3
When READ mode context B is selected (bit 3, Reg0x0C8 = 1):
0x0
Column
0: Normal readout.
Skip 2x — 1: READ out two columns, and then skip two columns (as with
Context B rows).
Bit 2
When READ mode context B is selected (bit 3, Reg0x0C8 = 1):
0x0
Row Skip 0: Normal readout.
2x—
1: READ out two rows, then skip two rows (i.e., row 8, row 9,
Context B row 12, row 13…).
Bit 1
Read out columns from right to left (mirrored). When set,
0x0
Mirror
column readout starts from column (Col Start + Col Size) and
Columns continues down to (Col Start + 1). When clear, readout starts at
Col Start and continues to (Col Start + Col Size - 1). This ensures
that the starting color is maintained.
Bit 0
Mirror
Rows
Read out rows from bottom to top (upside down). When set,
0x0
row readout starts from row (Row Start + Row Size) and
continues down to (Row Start + 1). When clear, readout starts at
Row Start and continues to (Row Start + Row Size - 1). This
ensures that the starting color is maintained.
R33:0—0x021 – Read Mode—Context A
Bit 10
When READ mode, context A is selected (bit 3, Reg0x0C8 = 0):
0x1
Low-Power 0: Full power, maximum readout speed.
Mode—
1: Low power. Maximum readout frequency is now half of the
Context A master clock, and the pixel clock is automatically adjusted as
described for the pixel clock speed register.
Bit 3
When READ mode context A is selected (bit 3, Reg0x0C8 = 0):
0x0
Column
0: Normal readout.
Skip 2x — 1: READ out two columns, and then skip two columns (as with
Context A rows).
Bit 2
When READ mode context A is selected (bit 3, Reg0x0C8 = 0):
0x0
Row Skip 0: Normal readout.
2x—
1: READ out two rows, and then skip two rows (i.e., row 8, row
Context A 9, row 12, row 13…).
R35:0—0x023 – Flash Control
Bit 15
READ only bit that indicates whether FLASH_STROBE is enabled. 0x0
Flash Strobe
Bit 14
Reserved.
—
SYNC’D TO
FRAME
START
Y
Y
Y
Y
Y
Y
Y
0
—
BAD READ/
FRAME WRITE
YM
W
YM
W
YM
W
YM
W
YM
W
YM
W
YM
W
0
R
—
—
Bit 13
Enable Xenon flash. When set, the FLASH_STROBE output signal 0x0
Y
N
W
Xenon Flash is pulsed HIGH for the programmed period during vertical
blanking. This is achieved by keeping the integration time equal
to one frame and the pulse width less than the vertical blanking
time.
Bits 12:11
Frame
Delay
Delay of the flash pulse measured in frames.
0x0
N
N
W
Bit 10
End of
Reset
0: In Xenon mode, the flash should be enabled after the
readout of a frame.
1: In Xenon mode, the flash should be triggered after the
resetting of a frame.
0x1
N
N
W
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
40
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