MT9V112 Datasheet, PDF (52/58 Pages) Micron Technology – SOC VGA DIGITAL IMAGE SENSOR

PRELIMINARY
MT9V112
SOC VGA DIGITAL IMAGE SENSOR
Appendix A
Serial Bus Description
Registers are written to and read from the MT9V112
through the two-wire serial interface bus. The sensor is
a serial interface slave controlled by the serial clock
(SCLK), which is driven by the serial interface master.
Data is transferred in and out of the MT9V112 through
the serial data (SDATA) line. The SDATA line is pulled up
to VDDQ off-chip by a 1.5KΩ resistor. Either the slave or
the master device can pull the SDATA line down—the
serial interface protocol determines which device is
allowed to pull the SDATA line down at any given time.
Protocol
The two-wire serial interface defines several differ-
ent transmission codes, as follows:
• a start bit
• a(an) (no) acknowledge bit
• an 8-bit message
• a stop bit
• the slave device 8-bit address
SADDR and R13:0[10] are used to select between two
different addresses in case of conflict with another
device. If SADDR XOR R13:0[10] is LOW, the slave
address is 0x90; if SADDR XOR R13:0[10] is HIGH, the
slave address is 0xBA. See Table 22.
Table 22: Two-Wire Interface ID
Address Switching
SADDR
0
0
1
1
R13:0[10]
0
1
0
1
TWO-WIRE INTERFACE
ADDRESS ID
0x90
0xBA
0xBA
0x90
Sequence
A typical read or write sequence begins with the
master sending a start bit. After the start bit, the mas-
ter sends the 8-bit slave device address. The last bit of
the address determines if the request is a READ or a
WRITE, where a “0” indicates a WRITE and a “1” indi-
cates a READ. The slave device acknowledges its
address by sending an acknowledge bit back to the
master.
If the request was a write, the master transfers the 8-
bit register address for where a write should take place.
The slave sends an acknowledge bit to indicate that the
register address has been received. The master then
transfers the data, 8 bits at a time, with the slave send-
ing an acknowledge bit after each eight bits.
The MT9V112 uses 16-bit data for its internal regis-
ters, thus requiring two 8-bit transfers to write to one
register. After 16 bits are transferred, the register
address is automatically incremented, so that the next
16 bits are written to the next register address. The
master stops writing by sending a start or stop bit.
A typical read sequence is executed as follows. The
master sends the write mode slave address and 8-bit
register address, just as in the write request. The mas-
ter then sends a start bit and the read mode slave
address. The master clocks out the register data, eight
bits at a time, and sends an acknowledge bit after each
8-bit transfer. The register address is auto-incre-
mented after every 16 bits is transferred. The data
transfer is stopped when the master sends a no-
acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines
are HIGH. Control of the bus is initiated with a start
bit, and the bus is released with a stop bit. Only the
master can generate the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition
of the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition
of the data line while the clock line is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device
consists of 7 bits of address and 1 bit of direction. A “0”
in the LSB of the address indicates write mode, and a
“1” indicates read mode. The write address of the sen-
sor is 0xBA; the read address is 0xBB. This applies only
when the SADDR is set HIGH.
Data Bit Transfer
One data bit is transferred during each clock pulse.
The serial interface clock pulse is provided by the mas-
ter. The data must be stable during the HIGH period of
the two-wire serial interface clock—it can only change
when the serial clock is LOW. Data is transferred 8 bits
at a time, followed by an acknowledge bit.
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MT9V112_2.fm- Rev. A 1/05 EN
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