PIC16F872_06 Datasheet, PDF(99/168 Page) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

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PIC16F872_06 Datasheet, PDF (99/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

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PIC16F872

11.10 Interrupts

The PIC16F872 has 10 sources of interrupt. The inter-

rupt control register (INTCON) records individual inter-

rupt requests in flag bits. It also has individual and

global interrupt enable bits.

Note:

Individual interrupt flag bits are set, regard-

less of the status of their corresponding

mask bit or the GIE bit.

A global interrupt enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interruptâs flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set,

regardless of the status of the GIE bit. The GIE bit is

cleared on RESET.

The âreturn from interruptâ instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

FIGURE 11-9:

EEIF

EEIE

INTERRUPT LOGIC

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the spe-

cial function registers, PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers, PIE1 and PIE2, and the peripheral

interrupt enable bit is contained in special function

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for one or two-cycle instructions. Individual

interrupt flag bits are set, regardless of the status of

their corresponding mask bit, PEIE bit, or GIE bit

ADIF

ADIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR0IF

TMR0IE

INTF

INTE

RBIF

RBIE

PEIE

GIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

TMR1IF

TMR1IE

BCLIF

BCLIE

DS30221C-page 97

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