PIC16F872_06 Datasheet, PDF (20/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

PIC16F872
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS: 0Dh)
U-0
R/W-0
U-0
—
reserved
—
bit 7
R/W-0
EEIF
R/W-0
BCLIF
U-0
U-0
R/W-0
—
— reserved
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I²C Master mode
0 = No bus collision has occurred
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS30221C-page 18
© 2006 Microchip Technology Inc.