PIC16F872_06 Datasheet, PDF (13/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

PIC16F872
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR,
on
BOR page:
Bank 2
100h⁽²⁾ INDF
101h TMR0
102h⁽²⁾ PCL
103h⁽²⁾ STATUS
104h⁽²⁾ FSR
105h
—
106h PORTB
107h
—
108h
—
109h
—
10Ah^(1,2) PCLATH
10Bh⁽²⁾ INTCON
10Ch EEDATA
10Dh EEADR
10Eh EEDATH
10Fh EEADRH
Addressing this location uses contents of FSR to address data memory
(not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
— Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
—
— EEPROM Data Register High Byte
—
—
— EEPROM Address Register High Byte
0000 0000 21, 93
xxxx xxxx 35, 93
0000 0000 20, 93
0001 1xxx 12, 93
xxxx xxxx 21, 93
—
—
xxxx xxxx 31, 93
—
—
—
—
—
—
---0 0000 20, 93
0000 000x 14, 93
xxxx xxxx 23, 94
xxxx xxxx 23, 94
xxxx xxxx 23, 94
xxxx xxxx 23, 94
Bank 3
180h⁽²⁾ INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
181h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 13, 94
182h⁽²⁾ PCL
Program Counter (PC) Least Significant Byte
0000 0000 20, 93
183h⁽²⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 12, 93
184h⁽²⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx 21, 93
185h
—
Unimplemented
—
—
186h TRISB
PORTB Data Direction Register
1111 1111 31, 94
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah^(1,2) PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
18Bh⁽²⁾ INTCON
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF 0000 000x 14, 93
18Ch EECON1
EEPGD
—
—
—
WRERR WREN WR
RD x--- x000 24, 94
18Dh EECON2
EEPROM Control Register2 (not a physical register)
---- ---- 23, 94
18Eh
—
Reserved; maintain clear
0000 0000 —
18Fh
—
Reserved; maintain clear
0000 0000 —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.
© 2006 Microchip Technology Inc.
DS30221C-page 11