PIC16F872_06 Datasheet, PDF (33/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

4.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the Low
Voltage Programming function; RB3/PGM, RB6/PGC
and RB7/PGD. The alternate functions of these pins
are described in the Special Features Section.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
RBPU⁽²⁾
Data Bus
WR Port
Data Latch
DQ
CK
VDD
Weak
P _Pull-up
I/O pin⁽¹⁾
WR TRIS
TRIS Latch
DQ
CK
TTL
Input
Buffer
RD TRIS
RD Port
QD
EN
RB0/INT
RB3/PGM
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
PIC16F872
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 11.10.1.
FIGURE 4-4:
RBPU⁽²⁾
Data Bus
WR Port
BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
Data Latch
DQ
CK
P
Weak
Pull-up
I/O pin⁽¹⁾
TRIS Latch
DQ
WR TRIS
CK
TTL
Input
Buffer
ST
Buffer
RD TRIS
RD Port
Set RBIF
Latch
QD
EN
Q1
From other
RB7:RB4 pins
RB7:RB6
In Serial Programming Mode
QD
EN
RD Port
Q3
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
© 2006 Microchip Technology Inc.
DS30221C-page 31