PIC16F872_06 Datasheet, PDF (73/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

PIC16F872
9.2.13 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG), and
the SCL pin is de-asserted high). When the SCL pin is
sampled high (clock arbitration), the baud rate genera-
tor counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off, and the SSP module
then goes into IDLE mode (Figure 9-16).
9.2.13.1 WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-16:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here.
Write to SSPCON2,
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
SDA
TBRG
TBRG
D0
ACK
SCL
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Note: TBRG = one baud rate generator period.
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
9.2.14 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit, by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-17).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
9.2.14.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
© 2006 Microchip Technology Inc.
DS30221C-page 71