PIC16F872_06 Datasheet, PDF (163/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

, RESET ........................................................................ 87 91
RESET Conditions for All Registers .......................... 93
RESET Conditions for PCON Register ...................... 93
RESET Conditions for Program Counter ................... 93
RESET Conditions for Special Registers .................. 93
RESET Conditions for STATUS Register .................. 93
RESET
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
WDT Reset. See Watchdog Timer (WDT)
Revision History ............................................................... 155
RSEN Bit
Repeated START Condition Enabled Bit (RSEN) ..... 54
S
S Bit
START Bit (S) ............................................................ 52
Sample Bit (SMP) .............................................................. 52
SCK Pin ............................................................................. 55
SCL Pin .............................................................................. 58
SDA Pin ............................................................................. 58
SDI Pin ............................................................................... 55
SDO Pin ............................................................................. 55
SEN Bit
START Condition Enabled Bit (SEN) ........................ 54
Serial Clock (SCK) ............................................................. 55
Serial Clock (SCL) ............................................................. 58
Serial Data Address (SDA) ................................................ 58
Serial Data In (SDI) ............................................................ 55
Serial Data Out (SDO) ....................................................... 55
Slave Select (SS) ............................................................... 55
SLEEP , ................................................................87 91, 100
SMP Bit .............................................................................. 52
Software Simulator (MPLAB SIM) ................................... 112
Special Features of the CPU ............................................. 87
Special Function Registers (SFRs) ...................................... 9
Data EEPROM and FLASH Program Memory .......... 23
Speed, Operating ................................................................. 1
SPI Clock Edge Select Bit (CKE) ....................................... 52
SPI Mode
Associated Registers ................................................. 57
Master Mode .............................................................. 56
Serial Clock ............................................................... 55
Serial Data In ............................................................. 55
Serial Data Out .......................................................... 55
Slave Select ............................................................... 55
SPI Clock ................................................................... 56
SS Pin ................................................................................ 55
SSBUF Register .................................................................. 9
MSSP
See also I²C Mode and SPI Mode.
SSPADD Register .............................................................. 10
SSPBUF register ............................................................... 58
SSPCON Register ............................................................... 9
SSPCON2 Register ........................................................... 10
SSPEN Bit ......................................................................... 53
, SSPIF ......................................................................... 16 59
SSPM3:SSPM0 Bits .......................................................... 53
, SSPOV Bit .................................................................. 53 59
SSPOV Status Flag ........................................................... 69
, SSPSTAT Register ..................................................... 10 58
Stack .................................................................................. 20
Overflows ................................................................... 20
Underflow .................................................................. 20
PIC16F872
, STATUS Register ..........................................................9 12
C Bit .......................................................................... 12
DC Bit ........................................................................ 12
IRP Bit ....................................................................... 12
, PD Bit ..................................................................12 91
RP1:RP0 Bits ............................................................ 12
, TO Bit ..................................................................12 91
Z Bit ........................................................................... 12
Synchronous Serial Port Enable Bit (SSPEN) ................... 53
Synchronous Serial Port Interrupt ..................................... 16
Synchronous Serial Port Mode Select Bits
(SSPM3:SSPM0) ...................................................... 53
T
T1CKPS0 bit ...................................................................... 39
T1CKPS1 bit ...................................................................... 39
T1CON Register .................................................................. 9
T1OSCEN bit ..................................................................... 39
T1SYNC bit ....................................................................... 39
T2CON Register .................................................................. 9
Time-out Sequence ........................................................... 92
Timer0 ............................................................................... 35
Associated Registers ................................................ 37
External Clock ........................................................... 36
Interrupt ..................................................................... 35
Overflow Flag (TMR0IF Bit) ...................................... 98
Overflow Interrupt ...................................................... 98
Prescaler ................................................................... 36
T0CKI ........................................................................ 36
Timer1 ............................................................................... 39
Associated Registers ................................................ 42
Asynchronous Counter Mode .................................... 41
Counter Operation ..................................................... 40
Operation in Timer Mode .......................................... 40
Oscillator ................................................................... 41
Capacitor Selection ........................................... 41
Prescaler ................................................................... 41
Reading and Writing in Asynchronous
Counter Mode ........................................... 41
Resetting of Timer1 Registers ................................... 41
Resetting Timer1 using a CCP Trigger Output ......... 41
Synchronized Counter Mode ..................................... 40
Timer2 ............................................................................... 43
Associated Registers ................................................ 44
Output ....................................................................... 44
Postscaler ................................................................. 43
Prescaler ................................................................... 43
Prescaler and Postscaler .......................................... 44
Timing Diagrams
A/D Conversion ....................................................... 137
Acknowledge Sequence ............................................ 71
Baud Rate Generator with Clock Arbitration ............. 65
BRG Reset Due to SDA Collision During
START Condition ...................................... 75
Brown-out Reset ..................................................... 129
Bus Collision
Transmit and Acknowledge ............................... 73
Bus Collision During a Repeated START
Condition (Case 1) .................................... 76
Bus Collision During a Repeated START
Condition (Case2) ..................................... 76
Bus Collision During a STOP Condition
(Case 1) .................................................... 77
Bus Collision During a STOP Condition
(Case 2) .................................................... 77
© 2006 Microchip Technology Inc.
DS30221C-page 161