PIC16F872_06 Datasheet, PDF (11/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

PIC16F872
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR,
on
BOR page:
Bank 0
00h⁽²⁾ INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
01h
TMR0
Timer0 Module Register
xxxx xxxx 35, 93
02h⁽²⁾ PCL
Program Counter (PC) Least Significant Byte
0000 0000 20, 93
03h⁽²⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 12, 93
04h⁽²⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx 21, 93
05h
PORTA
—
— PORTA Data Latch when written: PORTA pins when read
--0x 0000 29, 93
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 31, 93
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx 33, 93
08h
—
Unimplemented
—
—
09h
0Ah^(1,2)
0Bh⁽²⁾
—
PCLATH
INTCON
Unimplemented
—
—
GIE
PEIE
—
TMR0IE
—
—
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
INTE
RBIE TMR0IF INTF
RBIF 0000 000x 14, 93
0Ch
PIR1
(3)
ADIF
(3)
(3)
SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 16, 93
0Dh
PIR2
—
(3)
—
EEIF
BCLIF
—
—
(3) -r-0 0--r 18, 93
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 40, 94
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 40, 94
10h
T1CON
—
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 39, 94
11h
TMR2
Timer2 Module Register
0000 0000 43, 94
12h
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 43, 94
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 55, 94
14h
SSPCON
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 53, 94
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx 45, 94
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx 45, 94
17h
CCP1CON
—
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 45, 94
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx 84, 94
1Fh
ADCON0
ADCS1 ADCS0 CHS2
CHS1
CHS0
GO/
DONE
—
ADON _{0000 00-0 79, 94}
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.
© 2006 Microchip Technology Inc.
DS30221C-page 9