PIC16F872_06 Datasheet, PDF (47/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

PIC16F872
8.0 CAPTURE/COMPARE/PWM
MODULE
The Capture/Compare/PWM (CCP) module contains a
16-bit register, which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
The timer resources used by the module are shown in
Table 8-1.
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note (AN594),
“Using the CCP Modules” (DS00594).
TABLE 8-1: CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Capture
Compare
PWM
Timer Resource
Timer1
Timer1
Timer2
REGISTER 8-1:
CCP1CON REGISTER (ADDRESS: 17h)
U-0
—
bit 7
U-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as '0'
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS30221C-page 45