PIC16F872_06 Datasheet, PDF (57/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

9.1 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (IDLE state of SCK)
• Data input sample phase
(middle or end of data output time)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 9-4 shows the block diagram of the MSSP mod-
ule when in SPI mode.
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set, and
• Register ADCON1 must be set in a way that pin
RA5 is configured as a digital I/O
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
PIC16F872
FIGURE 9-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
SDI
SDO
SS
SCK
SSPSR reg
bit0
Shift
Clock
SS Control
Enable
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE ₄
2
TMR2 Output
2
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
Data Direction bit
9.1.1 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
© 2006 Microchip Technology Inc.
DS30221C-page 55