PIC16F872_06 Datasheet, PDF (137/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

PIC16F872
FIGURE 14-15: I²C BUS DATA TIMING
103
100
101
SCL
SDA
In
90
91
106
107
109
109
SDA
Out
Note: Refer to Figure 14-3 for load conditions.
102
92
110
TABLE 14-8: I²C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time
100 kHz mode
4.0
—
μs Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
0.6
—
μs Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
101 TLOW Clock Low Time
100 kHz mode
4.7
—
μs Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
μs Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
102 TR
SDA and SCL Rise
Time
100 kHz mode
400 kHz mode
—
1000
20 + 0.1CB 300
ns
ns CB is specified to be from
10 to 400 pF
103 TF
SDA and SCL Fall
Time
100 kHz mode
400 kHz mode
—
300
20 + 0.1CB 300
ns
ns CB is specified to be from
10 to 400 pF
90
TSU:STA START Condition
Setup Time
100 kHz mode
400 kHz mode
4.7
—
μs Only relevant for Repeated
0.6
—
μs ^{START condition}
91 THD:STA START Condition Hold 100 kHz mode
Time
400 kHz mode
4.0
—
μs After this period, the first clock
0.6
—
μs ^{pulse is generated}
106 THD:DAT Data Input Hold Time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
107 TSU:DAT Data Input Setup Time 100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
92
TSU:STO STOP Condition
Setup Time
100 kHz mode
400 kHz mode
4.7
—
μs
0.6
—
μs
109 TAA
Output Valid From
Clock
100 kHz mode
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
110 TBUF Bus Free Time
100 kHz mode
400 kHz mode
4.7
—
μs Time the bus must be free before
1.3
—
μs ^{a new transmission can start}
CB
Bus Capacitive Loading
—
400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode (400 kHz) I²C bus device can be used in a standard mode (100 kHz) I²C bus system, but the requirement
that TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line:
TR max.+ TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I²C bus specification) before the SCL line is
released.
© 2006 Microchip Technology Inc.
DS30221C-page 135