PIC16F872_06 Datasheet, PDF (71/168 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D

9.2.12 I²C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note:
The SSP module must be in an IDLE state
before the RCEN bit is set, or the RCEN bit
will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high), and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an Acknowledge
bit at the end of reception, by setting the Acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
PIC16F872
9.2.12.1 BF Status Flag
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
9.2.12.2 SSPOV Status Flag
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
9.2.12.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
© 2006 Microchip Technology Inc.
DS30221C-page 69