PIC18F86K22-I Datasheet, PDF (98/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY (CONTINUED)
Addr.
Name
Addr.
Name
Addr.
Name
Addr. Name Addr.
Name
Addr.
Name⁽⁴⁾
F3Fh
F3Eh
F3Dh
F3Ch
F3Bh
TMR7H⁽³⁾
TMR7L⁽³⁾
T7CON⁽³⁾
T7GCON⁽³⁾
TMR6
F32h
F31h
F30h
F2Fh
F2Eh
TMR12⁽³⁾
PR12⁽³⁾
T12CON⁽³⁾
CM2CON
CM3CON
F25h
F24h
F23h
F22h
F21h
ANCON0
ANCON1
ANCON2
RCSTA2
TXSTA2
F18h
F17h
F16h
PMD1
PMD2
PMD3
F3Ah
PR6
F2Dh CCPTMRS0 F20h BAUDCON2
F39H
F38h
T6CON
TMR8
F2Ch CCPTMRS1 F1Fh SPBRGH2
F2Bh CCPTMRS2 F1Eh SPBRG2
F37h
PR8
F2Ah REFOCON F1Dh RCREG2
F36h
F35h
F34h
F33h
T8CON
TMR10⁽³⁾
PR10⁽³⁾
T10CON⁽³⁾
F29H ODCON1
F28h ODCON2
F27h ODCON3
F26h MEMCON⁽³⁾
F1Ch TXREG2
F1Bh PSTR2CON
F1Ah PSTR3CON
F19h PMD0
Note 1:
2:
3:
4:
This is not a physical register.
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
This register is not available on devices with a program memory of 32 Kbytes (PIC18FX5K22).
Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers,
users must always load the proper BSR value.
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
Note 1:
2:
3:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
TOSH
Top-of-Stack High Byte (TOS<15:8>)
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
STKPTR
STKFUL STKUNF
—
Return Stack Pointer
PCLATU
—
—
—
Holding Register for PC<20:16>
PCLATH
Holding Register for PC<15:8>
PCL
PC Low Byte (PC<7:0>)
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
Program Memory Table Latch
PRODH
Product Register High Byte
PRODL
Product Register Low Byte
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of
FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
WREG
Working Register
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
---- ----
---- ----
---- ----
---- ----
---- ----
---- 0000
xxxx xxxx
xxxx xxxx
---- ----
DS39960D-page 98
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