PIC18F86K22-I Datasheet, PDF (313/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
21.4.7 BAUD RATE
In I²C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 21-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I²C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 21-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD. The SSPxADD BRG value of 0x00 is not
supported.
21.4.7.1 Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I²C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
FIGURE 21-19: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPxADD<6:0>
SSPM<3:0>
SCLx
Reload
Control
Reload
CLKO
BRG Down Counter
FOSC/4
TABLE 21-3: I²C™ CLOCK RATE w/BRG
FOSC
FCY
FCY * 2
40 MHz
10 MHz
20 MHz
40 MHz
10 MHz
20 MHz
40 MHz
10 MHz
20 MHz
16 MHz
4 MHz
8 MHz
16 MHz
4 MHz
8 MHz
16 MHz
4 MHz
8 MHz
4 MHz
1 MHz
2 MHz
4 MHz
1 MHz
2 MHz
16 MHz
4 MHz
8 MHz
Note 1: A minimum of 16 MHz FOSC is required to get 1 MHz I²C.
BRG Value
18h
1Fh
63h
09h
0Ch
27h
02h
09h
03h
FSCL
(2 Rollovers of BRG)
400 kHz
312.5 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
1 MHz⁽¹⁾
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