PIC18F86K22-I Datasheet, PDF (65/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
REGISTER 4-1: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3
R/W-0
CCP10MD⁽¹⁾
bit 7
R/W-0
CCP9MD⁽¹⁾
R/W-0
CCP8MD
R/W-0
CCP7MD
R/W-0
CCP6MD
R/W-0
CCP5MD
R/W-0
CCP4MD
R/W-0
TMR12MD⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CCP10MD: PMD CCP10 Enable/Disable bit⁽¹⁾
1 = Peripheral Module Disable (PMD) is enabled for CCP10, disabling all of its clock sources
0 = PMD is disabled for CCP10
bit 6
CCP9MD: PMD CCP9 Enable/Disable bit⁽¹⁾
1 = Peripheral Module Disable (PMD) is enabled for CCP9, disabling all of its clock sources
0 = PMD is disabled for CCP9
bit 5
CCP8MD: PMD CCP8 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP8, disabling all of its clock sources
0 = PMD is disabled for CCP8
bit 4
CCP7MD: PMD CCP7 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP7, disabling all of its clock sources
0 = PMD is disabled for CCP7
bit 3
CCP6MD: PMD CCP6 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP6, disabling all of its clock sources
0 = PMD is disabled for CCP6
bit 2
CCP5MD: PMD CCP5 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP5, disabling all of its clock sources
0 = PMD is disabled for CCP5
bit 1
CCP4MD: PMD CCP4 Enable/Disable bit
1 = Peripheral Module Disable (PMD) is enabled for CCP4, disabling all of its clock sources
0 = PMD is disabled for CCP4
bit 0
TMR12MD: TMR12MD Disable bit⁽¹⁾
1 = PMD is enabled and all TMR12MD clock sources are disabled
0 = PMD is disabled and TMR12MD is enabled
Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
 2009-2011 Microchip Technology Inc.
DS39960D-page 65