PIC18F86K22-I Datasheet, PDF (154/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
REGISTER 11-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
U-0
TMR5GIE
—
bit 7
R-0
RC2IE
R-0
TX2IE
R/W-0
CTMUIE
R/W-0
CCP2IE
R/W-0
CCP1IE
R/W-0
RTCCIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
RC2IE: EUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
REGISTER 11-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0
CCP10IE⁽¹⁾
bit 7
R/W-0
CCP9IE⁽¹⁾
R/W-0
CCP8IE
R/W-0
CCP7IE
R/W-0
CCP6IE
R/W-0
CCP5IE
R/W-0
CCP4IE
R/W-0
CCP3IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
CCP<10:3>IE: CCP<10:3> Interrupt Enable bits⁽¹⁾
1 = Enabled
0 = Disabled
Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
DS39960D-page 154
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