PIC18F86K22-I Datasheet, PDF (61/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
Clocks to the device continue while the INTOSC source
stabilizes after an interval of TIOBST (Parameter 39,
Table 31-13).
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
LF-INTOSC
OSC1
1
2
3
n-1 n
Clock Transition⁽¹⁾
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
Note 1: Clock transition typically occurs within 2-4 TOSC.
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
INTOSC
Multiplexer
OSC1
PLL Clock
Output
Q1
Q2
Q3
Q4
TOST⁽¹⁾
TPLL⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
SCS<1:0> bits Changed
OSTS bit Set
Q1
Q2 Q3 Q4 Q1 Q2 Q3
1 2 n-1 n
Clock
Transition⁽²⁾
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
 2009-2011 Microchip Technology Inc.
DS39960D-page 61