PIC18F86K22-I Datasheet, PDF (188/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
TABLE 12-17: PORTJ FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RJ0/ALE
RJ0
0
O
DIG LATJ<0> data output.
1
I
ST PORTJ<0> data input.
ALE
x
O
DIG External memory interface address latch enable control output; takes
priority over digital I/O.
RJ1/OE
RJ1
0
O
DIG LATJ<1> data output.
1
I
ST PORTJ<1> data input.
OE
x
O
DIG External memory interface output enable control output; takes priority
over digital I/O.
RJ2/WRL
RJ2
0
O
DIG LATJ<2> data output.
1
I
ST PORTJ<2> data input.
WRL
x
O
DIG External Memory Bus write low byte control; takes priority over
digital I/O.
RJ3/WRH
RJ3
0
O
DIG LATJ<3> data output.
1
I
ST PORTJ<3> data input.
WRH
x
O
DIG External memory interface write high-byte control; takes priority over
digital I/O.
RJ4/BA0
RJ4
0
O
DIG LATJ<4> data output.
1
I
ST PORTJ<4> data input.
BA0
x
O
DIG External Memory Interface Byte Address 0 control output; takes
priority over digital I/O.
RJ5/CE
RJ5
0
O
DIG LATJ<5> data output.
1
I
ST PORTJ<5> data input.
CE
x
O
DIG External memory interface chip enable control output; takes priority
over digital I/O.
RJ6/LB
RJ6
0
O
DIG LATJ<6> data output.
1
I
ST PORTJ<6> data input.
LB
x
O
DIG External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7/UB
RJ7
0
O
DIG LATJ<7> data output.
1
I
ST PORTJ<7> data input.
UB
x
O
DIG External memory interface upper byte enable control output; takes
priority over digital I/O.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 12-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTJ⁽¹⁾
RJ7
RJ6
RJ5
RJ4
RJ3
LATJ⁽¹⁾
LATJ7
LATJ6
LATJ5
LATJ4
LATJ3
TRISJ⁽¹⁾
TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3
PADCFG1
RDPU
REPU RJPU⁽¹⁾
—
—
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
RJ2
RJ1
LATJ2
LATJ1
TRISJ2
TRISJ1
RTSECSEL1 RTSECSEL0
Bit 0
RJ0
LATJ0
TRISJ0
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DS39960D-page 188
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