PIC18F86K22-I Datasheet, PDF (546/550 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers

PIC18F87K22 FAMILY
Transition for Two-Speed Start-up
(INTOSC to HSPLL).......................................... 423
Transition for Wake from Idle to Run Mode ................ 63
Transition for Wake from Sleep (HSPLL).................... 62
Transition from RC_RUN Mode to
PRI_RUN Mode .................................................. 61
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 59
Transition to RC_RUN Mode ...................................... 61
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements .................... 513
CLKO and I/O Requirements ............................ 505, 507
EUSART/AUSART Synchronous Receive
Requirements.................................................... 522
EUSART/AUSART Synchronous Transmission
Requirements.................................................... 522
Example SPI Mode Requirements (Master Mode,
CKE = 0) ........................................................... 514
Example SPI Mode Requirements (Master Mode,
CKE = 1) ........................................................... 515
Example SPI Mode Requirements (Slave Mode,
CKE = 0) ........................................................... 516
Example SPI Slave Mode Requirements
(CKE = 1) .......................................................... 517
External Clock Requirements ................................... 503
HLVD Characteristics................................................ 511
I²C Bus Data Requirements (Slave Mode) ............... 519
I²C Bus Start/Stop Bits Requirements
(Slave Mode)..................................................... 518
Internal RC Accuracy (INTOSC) ............................... 504
MSSP I²C Bus Data Requirements .......................... 521
MSSP I²C Bus Start/Stop Bits Requirements ........... 520
PLL Clock.................................................................. 504
Program Memory Fetch Requirements (8-bit)........... 506
Program Memory Write Requirements ..................... 508
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ......................................... 510
Timer0 and Timer1 External Clock Requirements .... 512
Top-of-Stack Access ........................................................... 89
TSTFSZ............................................................................. 471
Two-Speed Start-up .................................................. 403, 423
IESO (CONFIG1H, Internal/External Oscillator
Switchover Bit ................................................... 406
Two-Word Instructions
Example Cases........................................................... 93
TXSTAx Register
BRGH Bit .................................................................. 331
U
Ultra Low-Power Wake-up
Exit Delay ................................................................... 71
Overview..................................................................... 70
V
Voltage Reference Specifications..................................... 500
W
Watchdog Timer (WDT)............................................ 403, 419
Associated Registers ................................................ 420
Control Register........................................................ 420
During Oscillator Failure ........................................... 424
Programming Considerations ................................... 419
WCOL ....................................................... 315, 316, 317, 320
WCOL Status Flag.................................... 315, 316, 317, 320
WWW Address ................................................................. 547
WWW, On-Line Support ....................................................... 8
X
XORLW............................................................................. 471
XORWF ............................................................................ 472
DS39960D-page 546
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