LAN8740A Datasheet, PDF (92/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
4.3.8 WAKEUP FILTER CONFIGURATION REGISTER A (WUF_CFGA)
Index (In Decimal): 3.32785
Size:
16 bits
Bits
15
14
13:11
10
9
8
7:0
Description
Filter Enable
0 = Filter disabled
1 = Filter enabled
Filter Triggered
0 = Filter not triggered
1 = Filter triggered
RESERVED
Address Match Enable
When set, the destination address must match the programmed address.
When cleared, any unicast packet is accepted. Refer to Section 3.8.4.4,
"Wakeup Frame Detection" for additional information.
Filter Any Multicast Enable
When set, any multicast packet other than a broadcast will cause an address
match. Refer to Section 3.8.4.4, "Wakeup Frame Detection" for additional
information.
Note: This bit has priority over bit 10 of this register.
Filter Broadcast Enable
When set, any broadcast frame will cause an address match. Refer to Section
3.8.4.4, "Wakeup Frame Detection" for additional information.
Note: This bit has priority over bit 10 of this register.
Filter Pattern Offset
Specifies the offset of the first byte in the frame on which CRC checking
begins for Wakeup Frame recognition. Offset 0 is the first byte of the incoming
frame’s destination address.
Type
R/W/
NASR
R/WC/
NASR
RO
R/W/
NASR
R/W/
NASR
R/W/
NASR
R/W/
NASR
Default
0b
0b
-
0b
0b
0b
00h
DS00001987A-page 92
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