LAN8740A Datasheet, PDF(9/136 Page) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

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LAN8740A Datasheet, PDF (9/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

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LAN8740A/LAN8740Ai

TABLE 2-1: MII/RMII SIGNALS (CONTINUED)

Num Pins

Name

Receive

Data 3

(MII Mode)

PHY Address 2

Configuration

Strap

Symbol

RXD3

PHYAD2

Receive Error

RXER

Receive

Data 4

(MII Mode)

RXD4

PHY Address 0

Configuration

Strap

PHYAD0

Receive Clock

RXCLK

(MII Mode)

PHY Address 1

Configuration

Strap

PHYAD1

Receive Data

RXDV

Valid

Buffer Type

Description

VO8

Bit 3 of the 4 (in MII mode) data bits that are sent by

the transceiver on the receive path.

VIS

(PD)

Note: This signal is not used in RMII mode.

Combined with PHYAD0 and PHYAD1, this config-

uration strap sets the transceiverâs SMI address.

VO8

VIS

(PD)

See Note 1 for more information on configuration

straps.

Note:

Refer to Section 3.7.1, "PHYAD[2:0]:

PHY Address Configuration" for addi-

tional information.

This signal is asserted to indicate that an error was

detected somewhere in the frame presently being

transferred from the transceiver. This signal is also

used in EEE mode as RXER when RXDV = 1, and

as LPI when RXDV = 0.

Note: This signal is optional in RMII mode.

In Symbol Interface (5B decoding) mode, this sig-

nal is the MII Receive Data 4 signal, the MSB of the

received 5-bit symbol code-group.

Note: Unless configured to the Symbol Inter-

face mode, this pin functions as RXER.

Combined with PHYAD1 and PHYAD2, this config-

uration strap sets the transceiverâs SMI address.

VO8

VIS

(PD)

See Note 1 for more information on configuration

straps.

Note:

Refer to Section 3.7.1, "PHYAD[2:0]:

PHY Address Configuration" for addi-

tional information.

In MII mode, this pin is the receive clock output.

â¢ MII (100BASE-TX): 25 MHz

â¢ MII (10BASE-T): 2.5 MHz

Combined with PHYAD0 and PHYAD2, this config-

uration strap sets the transceiverâs SMI address.

VO8

See Note 1 for more information on configuration

straps.

Note:

Refer to Section 3.7.1, "PHYAD[2:0]:

PHY Address Configuration" for addi-

tional information.

Indicates that recovered and decoded data is avail-

able on the RXD pins.

ï£ 2013-2015 Microchip Technology Inc.

DS00001987A-page 9

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